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general description the max5713/max5714/max5715 4-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (dacs) include output buffers and an internal reference that is selectable to be 2.048v, 2.500v, or 4.096v. the max5713/max5714/max5715 accept a wide supply voltage range of 2.7v to 5.5v with extremely low power (3mw) consumption to accommodate most low-voltage applications. a precision external reference input allows rail-to-rail operation and presents a 100k i (typ) load to an external reference. the max5713/max5714/max5715 have a 50mhz 3-wire spi/qspi?/microwire?/dsp-compatible serial interface that also includes a rdy output for daisy-chain applica- tions. the dac outp ut is buffered and has a low supply current of less than 250fa per channel and a low off- set error of q0.5mv (typ). on power-up, the max5713/ max5714/max5715 reset the dac outputs to zero, pro- viding additional safety for applications that drive valves or other transducers which need to be off on power-up. the internal reference is initially powered down to allow use of an external reference. the max5713/max5714/ max5715 allow simultaneous output updates using soft- ware load commands or the hardware load dac logic input (ldac). a clear logic input (clr) allows the contents of the code and the dac registers to be cleared asynchronously and sets the dac outputs to zero. the max5713/max5714/ max5715 are available in a 14-pin tssop and an ultra- small, 12-bump wlp package and are specified over the -40nc to +125nc temperature range. applications programmable voltage and current sources gain and offset adjustment automatic tuning and optical control power amplifier control and biasing process control and servo loops portable instrumentation data acquisition benefits and features s four high-accuracy dac channels ? 12-bit accuracy without adjustment ? 1 lsb inl buffered voltage output ? monotonic over all operating conditions ? independent mode settings for each dac s three precision selectable internal references ? 2.048v, 2.500v, or 4.096v s internal output buffer ? rail-to-rail operation with external reference ? 4.5s settling time ? outputs directly drive 2ki loads s small 5mm x 4.4mm 14-pin tssop or ultra-small 1.6mm x 2.2mm 12-bump wlp package s wide 2.7v to 5.5v supply range s separate 1.8v to 5.5v v ddio power-supply input s 50mhz 3-wire spi/qspi/microwire/dsp compatible serial interface with rdy output s power-on-reset to zero-scale dac output s ldac and clr for asynchronous control s three software-selectable power-down output impedances ? 1ki, 100ki, or high impedance 19-6394; rev 2; 1/13 ordering information appears at end of data sheet. functional diagram qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation. max is a registered trademark of maxim integrated products, inc. din sclk csb outa buffer por v dd gnd dac control logic power-down ref outb outc outd v ddio (rdy) clr (ldac) spi serial interface ( ) tssop package only 1ki 100ki code load clear / reset clear / reset code register dac latch 8- /1 0- / 12-bit dac 1 of 4 dac channels internal reference/ external buffer max5713 max5714 max5715 for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max5713.related max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 v dd , v ddio to gnd ................................................ -0.3v to +6v out_, ref to gnd ................................. ....-0.3v to the lower of (v dd + 0.3v) and +6v csb, sclk, ldac, clr to gnd ............................ -0.3v to +6v din, rdy to gnd ........................................ -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70nc) tssop (derate at 10mw/nc above 70nc) ................... 797mw wlp (derate at 16.1mw/nc above 70nc) .................. 1288mw maximum continuous current into any pin .................... q50ma operating temperature range ........................ -40nc to +125nc storage temperature range ............................ -65nc to +150nc lead temperature (tssop only)(soldering, 10s) ........... +300nc soldering temperature (reflow) .................................... +260nc tssop junction-to-ambient thermal resistance ( ja ) ....... 100nc/w junction-to-case thermal resistance ( jc ) ............... 30nc/w wlp junction-to-ambient thermal resistance ( ja ) (note 2) ........................................................................ 62nc/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. note 2: visit www.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of wlp packaging. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units dc performance (note 4) resolution and monotonicity n max5713 8 bits max5714 10 max5715 12 integral nonlinearity (note 5) inl max5713 -0.25 q0.05 +0.25 lsb max5714 -0.5 q0.25 +0.5 max5715 -1 q0. 5 +1 differential nonlinearity (note 5) dnl max5713 -0.25 q0.05 +0.25 lsb max5714 -0.5 q0.1 +0.5 max5715 -1 q0.2 +1 offset error (note 6) oe -5 q0.5 +5 mv offset error drift q10 fv/nc gain error (note 6) ge -1.0 q0.1 +1.0 %fs gain temperature coefficient with respect to v ref q3.0 ppm of fs/nc zero-scale error 0 10 mv full-scale error with respect to v ref -0.5 +0.5 %fs maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units dac output characteristics output voltage range (note 7) no load 0 v dd v 2ki load to gnd 0 v dd - 0.2 2ki load to v dd 0.2 v dd load regulation v out = v fs /2 v dd = 3v q10%, |i out | p 5ma 300 fv/ma v dd = 5v q10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q10%, |i out | p 5ma 0.3 i v dd = 5v q10%, |i out | p 10ma 0.3 maximum capacitive load handling c l 500 pf resistive load handling r l 2 ki short-circuit output current v dd = 5.5v sourcing (output shorted to gnd) 30 ma sinking (output shorted to v dd ) 50 dc power-supply rejection v dd = 3v q10% or 5v q10% 100 fv/v dynamic performance voltage-output slew rate sr positive and negative 1.0 v/fs voltage-output settling time ? scale to ? scale, to p 1 lsb, max5713 2.2 fs ? scale to ? scale, to p 1 lsb, max5714 2.6 ? scale to ? scale, to p 1 lsb, max5715 4.5 dac glitch impulse major code transition 7 nv*s channel-to-channel feedthrough (note 8) external reference 3.5 nv*s internal reference 3.3 digital feedthrough code = 0, all digital inputs from 0v to v ddio 0.2 nv*s power-up time startup calibration time (note 9) 200 fs from power-down 50 fs maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units output voltage-noise density (dac output at midscale) external reference f = 1khz 90 nv/hz f = 10khz 82 2.048v internal reference f = 1khz 112 f = 10khz 102 2.5v internal reference f = 1khz 125 f = 10khz 110 4.096v internal reference f = 1khz 160 f = 10khz 145 integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 12 fv p-p f = 0.1hz to 10khz 76 f = 0.1hz to 300khz 385 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 91 f = 0.1hz to 300khz 450 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 470 4.096v internal reference f = 0.1hz to 10hz 16 f = 0.1hz to 10khz 124 f = 0.1hz to 300khz 490 output voltage-noise density (dac output at full scale) external reference f = 1khz 114 nv/hz f = 10khz 99 2.048v internal reference f = 1khz 175 f = 10khz 153 2.5v internal reference f = 1khz 200 f = 10khz 174 4.096v internal reference f = 1khz 295 f = 10khz 255 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 13 fv p-p f = 0.1hz to 10khz 94 f = 0.1hz to 300khz 540 2.048v internal reference f = 0.1hz to 10hz 19 f = 0.1hz to 10khz 143 f = 0.1hz to 300khz 685 2.5v internal reference f = 0.1hz to 10hz 21 f = 0.1hz to 10khz 159 f = 0.1hz to 300khz 705 4.096v internal reference f = 0.1hz to 10hz 26 f = 0.1hz to 10khz 213 f = 0.1hz to 300khz 750 maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 74 fa reference input impedance r ref 75 100 ki reference ouput reference output voltage v ref v ref = 2.048v, t a = +25nc 2.043 2.048 2.053 v v ref = 2.5v, t a = +25nc 2.494 2.500 2.506 v ref = 4.096v, t a = +25nc 4.086 4.096 4.106 reference temperature coefficient (note 10) max5715a q3.7 q10 ppm/nc max5713/max5714/max5715b q10 q25 reference drive capacity external load 25 ki reference capacitive load 200 pf reference load regulation i source = 0 to 500fa 2 mv/ma reference line regulation 0.05 mv/v power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 i/o supply voltage v ddio 1.8 5.5 v supply current (note 11) i dd internal reference v ref = 2.048v 0.93 1.25 ma v ref = 2.5v 0.98 1.30 v ref = 4.096v 1.16 1.50 external reference v ref = 3v 0.85 1.15 v ref = 5v 1.10 1.40 interface supply current (note 11) i ddio 1 fa power-down mode supply current i pd all dacs off, internal reference on 140 fa all dacs off, internal reference off, t a = -40nc to +85nc 0.5 1 all dacs off, internal reference off, t a = +125nc 1.2 2.5 digital input chracteristics (csb, sclk, din, ldac, clr) hysteresis voltage v h 0.15 v input high voltage v il 2.2v < v ddio < 5.5v 0.7x v ddio v 1.8v < v ddio < 2.2v 0.8x v ddio maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units input low voltage (note 11) v il 2.2v < v ddio < 5.5v 0.3 x v ddio v 1.8v < v ddio < 2.2v 0.2 x v ddio input leakage current i in v in = 0v or v ddio (note 11) q0.1 q1 fa input capacitance (note 10) c in 10 pf digital output (rdy) output high voltage v oh v ddio > 2.5v, i source = 3ma v ddio - 0.2 v v ddio > 1.8v, i source = 2ma v ddio - 0.2 v output low voltage v ol v ddio > 2.5v, i sink = 3ma 0.2 v v ddio > 1.8v, i sink = 2ma 0.2 v output short-circuit current i oss i sink , i source 100 ma spi timing characteristics (csb, sclk, din, rdy) sclk frequency f sclk 2.7v < v ddio < 5.5v, standalone, daisy chain (note 12) 0 50 mhz 0 20 1.8v < v ddio < 2.7v, standalone, daisy chain (note 12) 0 33 0 20 sclk period t sclk 2.7v < v ddio < 5.5v 20 ns 1.8v < v ddio < 2.7v 30 sclk pulse width high t ch 8 ns sclk pulse width low t cl 8 ns csb fall to sclk fall setup time t css0 to first sclk falling edge 8 ns csb fall to sclk fall hold time t csh0 applies to inactive sclk falling edge preceding the first sclk falling edge 0 ns csb rise to sclk fall hold time t csh1 applies to the 24th sclk falling edge 0 ns csb rise to sclk fall t csa applies to the 24th sclk falling edge, aborted sequence 12 ns sclk fall to csb fall t csf applies to 24th sclk falling edge 100 ns csb pulse width high t cspw 20 ns din to sclk fall setup time t ds 5 ns din to sclk fall hold time t dh 4.5 ns clr pulse width low t clpw 20 ns clr rise to csb fall t csc required for command to be executed 20 ns ldac pulse width low t ldpw 20 ns ldac fall to sclk fall hold t ldh a pplies to 24th sclk falling edge, 20 ns maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
7 note 3: electrical specifications are production tested at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization. typical specifications are at t a = +25c and are not guaranteed. note 4: dc performance is tested without load. note 5: linearity is tested with unloaded outputs to within 20mv of gnd and v dd . note 6: offset and gain errors are calculated from measurements made with v ref = v dd at code 30 and 4065 for max5715, code 8 and 1016 for max5714, and code 2 and 254 for max5713. note 7: subject to zero and full-scale error limits and v ref settings. note 8: measured with all other dac outputs at midscale with one channel transitioning 0 to full scale. note 9: on power-up, the device initiates an internal 200s (typ) calibration sequence. all commands issued during this time will be ignored. note 10: guaranteed by design. note 11: all channels active at v fs , unloaded. static logic inputs with v il = v gnd and v ih = v ddio . note 12: daisy-chain speed is relaxed to accommodate (t crf + t css0 ) with margin (derived specification, not production tested). note 13: this specification and its propagation through the chain limits how quickly an aborted daisy-chain command can be fol- lowed by another daisy-chain command, to be applied on a per-device basis. figure 1. spi serial interface timing diagram electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units sclk fall to rdy fall t crf a pplies to 24th sclk falling edge, c load = 20pf 40 ns sclk fall to rdy hold t crh a pplies to 24th sclk falling edge, c load = 0pf 2 ns csb rise to rdy rise t csr c load = 20pf (note 13) 40 ns d in 23 d in 22 d in 21 d in 20 d in 19 d in 18 d in 17 d in 16 d in 2 d in 1 t csa t csf t ldpw t ldh t csh1 d in 0 d in 23 1 sclk csb din 23 45 67 82 22 32 41 t csh0 t cspw t clpw t csc t css0 t ch t cl t dh t ds t sclk ldac clr maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
8 max5713/max5714/max5715 typical operating characteristics (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) figure 2. elongated spi serial interface timing diagram (daisy-chain applications, tssop package only) d in 23 x in clk csb rdy d in 22 d in 21 d in 20 d in 19 d in 18 d in 17 d in 16 d in 2 d in 1 d in 0 d in 23 123 45 67 82 22 32 4 t crh t csf t crf 25 t csr t ch t cl t sclk t ds t dh t csh0 t cspw t css0 inl vs. code max5713 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load inl vs. code max5713 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load dnl vs. code max5713 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load maxim integrated ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
9 typical operating characteristics (continued) (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) dnl vs. code max5713 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage max5713 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 max inl v ref = 2.7v 1.0 -1.0 2.7 5.5 max dnl min dnl min inl inl and dnl vs. temperature max5713 toc06 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (lsb) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 max inl v dd = v ref = 3v max dnl min dnl min inl offset and zero-scale error vs. supply voltage max5713 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 zero-scale error offset error v ref = 2.5v (external) no load offset and zero-scale error vs. temperature max5713 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error full-scale error and gain error vs. supply voltage max5713 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016 v ref = 2.5v (external) no load 0.020 -0.020 2.7 5.5 full-scale error gain error full-scale error and gain error vs. temperature max5713 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) -0.05 0 0.05 0.10 -0.10 v ref = 2.5v (external) no load gain error (v dd = 3v) gain error (v dd = 5v) full-scale error supply current vs. temperature max5713 toc11 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 supply current (ma) 0.6 0.8 1.0 1.4 1.2 0.4 out_ = full scale no load v ref (external) = v dd = 3v v ref (external) = v dd = 5v v ref (internal) = 2.5v, v dd = 5v v ref (internal) = 2.048v, v dd = 5v v ref (internal) = 4.096v, v dd = 5v supply current vs. supply voltage max5713 toc12 v dd (v) 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 v ref (internal) = 4.096v supply current (ma) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 no load t a = +25c v ref (internal) = 2.5v v ref (external) = 2.5v v ref (internal) = 2.048v maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
typical operating characteristics (continued) (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) 10 maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface power-down mode supply current vs. temperature max5713 toc13 supply voltage (v) 5.1 3.5 3.9 4.3 4.7 3.1 2.7 5.5 power-down supply current (a) 0.4 0.8 1.6 1.2 0 power-down mode all dacs t a = -40c t a = +25c t a = +85c t a = +125c supply current vs. code max5713 toc14 code (lsb) 4000 3500 3000 2500 2000 1500 1000 500 0 4500 supply current (ma) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 no load t a = +25c v dd = 5v, v ref (external) = 5v v dd = 5v, v ref (internal) = 4.096v v dd = 5v, v ref (internal) = 2.048v v dd = 5v, v ref (internal) = 2.5v v dd = 3v, v ref (external) = 3v i ref (external) vs. code max5713 toc15 code (lsb) reference current ( a) 3584 3072 2560 2048 1536 1024 10 20 30 40 50 60 0 512 0 4096 v dd = v ref no load v ref = 5v v ref = 3v max5713 toc17 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div 4.3s settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3/4 scale to 1/4 scal e max5713 toc16 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3.75s 1/4 scale to 3/4 scal e max5713 toc18 trigger pulse 5v/div 1 lsb change (midcode transition 0x7ff to 0x800) glitch energy = 6.7nv?s zoomed v out 3.3mv/div 2s/div major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf)
typical operating characteristics (continued) (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) 11 maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5713 toc19 2s/div trigger pulse 5v/div zoomed v out 3.3mv/div 1 lsb change (midcode transition 0x800 to 0x7ff) glitch energy = 6nv?s v out vs. time transient exiting power-down max5713 toc20 dac output 500mv/div 10s / div v sclk 5v/div 0v 0v v dd = 5v, v ref = 2.5v external 24th edge power-on reset to 0v max5713 toc21 v out 2v/div 20s / div v dd 2v/div 0v 0v v dd = v ref = 5v 10ki load to v dd channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, no load) max5713 toc23 5s / div no load no load trigger pulse 10v/div static dac 1.25mv/div transitioning dac 1v/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.8nv*s channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, r l = 2ki , c l = 200pf) max5713 toc22 4s / div trigger pulse 10v/div transitioning dac 1v/div r l = 2k i no load static dac 1.25mv/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.5nv*s channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, r l = 2ki , c l = 200pf) max5713 toc24 5s / div trigger pulse 10v/div no load static dac 1.25mv/div transitioning dac 1v/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s r l = 2k i
12 typical operating characteristics (continued) (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) max5713/max5714/max5715 max5713 toc25 trigger pulse 10v/div transitioning dac 1v/div static dac 1.25mv/div no load no load 4s/div channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, no load) transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.1nv*s max5713 toc26 400ns/div digital feedthrough v dd = v re f = 5v r l = 10k 0.7mv/div digital feedthrough -0.1nvs output load regulation max5713 toc27 i o ut (ma) d v out (mv) 50 40 20 30 -10 0 10 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -30 60 v dd = v ref v dd = 5v v dd = 3v headroom at rails vs. output current (v dd = v ref ) max5713 toc29 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 01 0 v dd = 5v, sourcing v dd = 3v, sourcing v dd = 3v and 5v sinking dac = zero scale dac = full scale output current limiting max5713 toc28 i out (ma) d v out (mv) 60 50 30 40 -10 0 10 20 -20 -400 -300 -200 -100 0 100 200 300 400 500 -500 -30 70 v dd = v ref v dd = 5v v dd = 3v noise-voltage density vs. frequency (dac at midscale) max5713 toc30 frequency (hz) noise-voltage density (nv/ hz) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 2.048v (internal) v dd = 5v, v ref = 4.5v (external) v dd = 5v, v ref = 4.096v (internal) v dd = 5v, v ref = 2.5v (internal) maxim integrated ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
13 typical operating characteristics (continued) (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) max5713 toc31 2v/div midscale unloaded v p-p = 12v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) max5713 toc32 2v/div midscale unloaded v p-p = 13v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.5v) max5713 toc33 2v/div midscale unloaded v p-p = 15v 4s /div v ref drift vs. temperature max5713 toc35 temperature drift (ppm /c) percent of population (%) 4.3 4.1 4.0 3.9 3.7 3.6 3.4 3.3 3.2 3.0 2.9 5 10 15 20 25 0 2.8 4.4 v dd = 2.7v, v ref (internal) = 2.5v box method 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) max5713 toc34 2v/div midscale unloaded v p-p = 16v 4s /div reference load regulation max5713 toc36 reference output current (a) dv ref (mv) 450 400 350 300 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 -1.0 0 500 v dd = 5v internal reference v ref = 2.048v, 2.5v, and 4.096v supply current vs. logic voltage max5713 toc37 input logic voltage (v) supply current (a) 4 3 2 1 300 600 900 1200 1500 1800 2100 2400 2700 3000 0 05 v ddio = 5v v ddio = 3v v ddio = 1.8v maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
14 pin/bump description pin/bump configurations pin bump name function tssop wlp 1 b1 ref reference voltage input/output 2 a1 outa buffered channel a dac output 3 a2 outb buffered channel b dac output 4 b2 gnd ground 5 a3 outc buffered channel c dac output 6 a4 outd buffered channel d dac output 7 b4 v dd supply voltage input. bypass v dd with a 0.1ff capacitor to gnd. 8 rdy spi rdy output. in daisy-chained applications connect rdy to the csb of the next device in the chain. 9 c4 din spi interface data input 10 c3 sclk spi interface clock input 11 c2 csb spi chip-select input 12 c1 clr active-low clear input 13 b3 v ddio digital interface power-supply input 14 ldac load dac. active-low hardware load dac input. 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ldac v ddio clr csb gnd outb outa ref top view max5713 max5714 max5715 sclk din rdy v dd outd outc tssop + wlp top view din clr v dd ref outd outa max5713/max5714/max5715 + 1 2 34 a csbs clk gnd v ddio outb outc b c maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
15 detailed description the max5713/max5714/max5715 are 4-channel, low- power, 8-/10-/12-bit buffered voltage-output dacs. the 2.7v to 5.5v wide supply voltage range and low-power consumption accommodates most low-power and low- voltage applications. the devices present a 100k i load to the external reference. the internal output buffers allow rail-to-rail operation. an internal voltage reference is available with software selectable options of 2.048v, 2.5v, or 4.096v. the devices feature a 50mhz, 3-wire spi/qspi/microwire/dsp-compatible serial interface to save board space and reduce the complexity in isolated applications. the max5713/max5714/max5715 include a serial-in/parallel-out shift register, internal code and dac registers, a power-on-reset (por) circuit to initialize the dac outputs to code zero, and control logic. clr is available to asynchronously clear the device indepen- dent of the serial interface. dac outputs (out_) the max5713/max5714/max5715 include internal buf- fers on all dac outputs. the internal output buffers provide improved load regulation for the dac outputs. the output buffers slew at 1v/fs (typ) and drive resistive loads as low as 2ki in parallel with as much as 500pf of capacitance.. the analog supply voltage (v dd ) deter- mines the maximum output voltage range of the devices as v dd powers the output buffer. under no-load condi - tions, the output buffers drive from gnd to v dd , subject to offset and gain errors. with a 2k load to gnd, the output buffers drive from gnd to within 200mv of v dd . with a 2k load to v dd , the output buffers drive from v dd to within 200mv of gnd. the dac ideal output voltage is defined by: out ref n d vv 2 = where d = code loaded into the dac register, v ref = reference voltage, n = resolution. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to control registers, individual, or multiple dacs as determined by the user command. within each dac channel there is a code register followed by a dac latch register (see the detailed functional diagram). the contents of the code register hold pending dac output settings which can later be loaded into the dac registers. the code register can be updated using both code and code_load user com- mands. the contents of the dac register hold the current dac output settings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands or the ldac hardware pin. the contents of both code and dac registers are main- tained during power-down states, so that when the dacs are powered on, they return to their previously stored output settings. any code or load commands issued during power-down states continue to update the register contents. sw_clear and sw_reset commands reset the contents of all code and dac registers to their zero- scale defaults. internal reference the max5713/max5714/max5715 include an internal precision voltage reference that is software selectable to be 2.048v, 2.500v, or 4.096v. when an internal refer- ence is selected, that voltage is available on the ref pin for other external circuitry (see the typical operating circuits) and can drive a 25ki load. external reference the external reference input has a typical input impedance of 100ki and accepts an input voltage from +1.24v to v dd . connect an external voltage supply between ref and gnd to apply an exter- nal reference. the max5713/max5714/max5715 power up and reset to external reference mode. visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. load dac (ldac) input (tssop package only) the max5713/max5714/max5715 feature an active- low ldac logic input that allows the outputs to update asynchronously. connect ldac to v ddio or keep ldac high during normal operation when the device is con - trolled only through the serial interface. drive ldac low to simultaneously update the dac outputs with data from the code registers. holding ldac low causes the dac registers to become transparent and code data is passed through to the dac registers immediately updat- ing the dac outputs. a software config command can be used to configure the ldac operation of each dac independently. maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
16 clear input (clr) the max5713/max5714/max5715 feature an asynchro- nous active-low clr logic input that simultaneously sets all four dac outputs to zero. driving clr low clears the contents of both the code and dac registers and also aborts the on-going spi command. to allow a new spi command, drive clr high, satisfying the t csc timing requirement. interface power supply (v ddio ) the max5713/max5714/max5715 feature a separate supply pin (v ddio ) for the digital interface (1.8v to 5.5v). connect v ddio to the i/o supply of the host processor. spi serial interface the max5713/max5714/max5715 3-wire serial interface is compatible with microwire, spi, qspi, and dsps. the interface provides three inputs, sclk, csb, and din. the chip-select input (csb, active low) frames the data loaded through the serial data input (din). following a csb input high-to-low transition, the data is shifted in synchronously and latched into the input register on each falling edge of the serial clock input (sclk). each serial operation word is 24-bits long. the dac data is left justified as shown in table 1. the serial input register transfers its contents to the destination registers after loading 24 bits of data on the 24th sclk falling edge. to initiate a new spi operation, drive csb high and then low to begin the next operation sequence, being sure to meet all relevant timing requirements. during csb high periods, sclk is ignored, allowing communication to other devices on the same bus. spi operations consist- ing of more than 24 sclk cycles are executed on the 24th sclk falling edge, using the first three bytes of data available. spi operations consisting of less than 24 sclk cycles will not be executed. the content of the spi operation consists of a command byte followed by a two byte data word. figure 1 shows the timing diagram for the complete 3-wire serial interface transmission. the dac code settings (d) for the max5713/max5714/max5715 are accepted in an offset binary format (see table 1). otherwise, the expected data format for each command is listed in table 2. see figure 3 for an example of a typi- cal spi circuit application. spi daisy chain/rdy output (tssop package only) the elongated programming operation is typically used for devices in daisy-chain applications. the rdy out- put in the tssop version of the max5713/max5714/ max5715 feeds the csb input of the next device in the daisy-chain. the max5713/max5714/max5715 pulls the rdy output low on the 24th sclk falling edge, allowing the next device in the chain to begin its spi operation, commencing with the 25th sclk falling edge. see figure 2 for timing characteristics of the elongated spi program- ming operation. in practice (t crf + t css0 ) requirements will limit the daisy-chain spi speed. also in daisy-chain applications, a partial write to the chain is possible as long as the t csa is met for the first device the user chooses not to program. see figure 4 for an example of a daisy-chain circuit application. table 1. format dac data bit positions part b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 max5713 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x max5714 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x max5715 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
17 spi user-command register map this section lists the user accessible commands and registers for the max5713/max5714/max5715. table 2 provides detailed information about the command registers. figure 4. typical spi daisy-chain application circuit figure 3. typical spi application circuit max5713 max5714 max5715 csb sclk din csb sclk din * csb sclk din *additional spi device csb1 sclk mosi c rdy rdy max5713 max5714 max5715 csb sclk din csb sclk din * * dout csb csb3 csb2 miso sclk din *additional spi device csb1 sclk mosi c maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
18 table 2. spi commands summary command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description dac commands coden 0 0 0 0 dac selection code register data [11:4] code register data [3:0] x x x x writes data to the selected code register(s) loadn 0 0 0 1 dac selection x x x x x x x x x x x x x x x x transfers data from the selected code register(s) to the selected dac register(s) coden_ load_all 0 0 1 0 dac selection code register data [11:4] code register data [3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers coden_ loadn 0 0 1 1 dac selection code register data [11:4] code register data [3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s) configuration commands power 0 1 0 0 0 0 power mode 00 = normal 01 = pd 1ki 10 = pd 100ki 11 = pd hi-z x x x x dac d dac c dac b dac a x x x x x x x x sets the power mode of the selected dacs (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) sw_clear 0 1 0 1 0 0 0 0 x x x x x x x x x x x x x x x x executes a software clear (all code and dac registers cleared to their default values) sw_reset 0 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x x executes a software reset (all code, dac, and control registers returned to their default values) maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
19 table 2. spi commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description config 0 1 1 0 all dacs 0 0 ld_en x x x x dac d dac c dac b dac a x x x x x x x x sets the dac latch mode of the selected dacs. only dacs with a 1 in the selection bit are updated by the command. ld_en = 0: dac latch is operational (load and ldac controlled) ld_en = 1: dac latch is transparent ref 0 1 1 1 0 ref power 0 = dac 1 = on ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v x x x x x x x x x x x x x x x x sets the reference operating mode. ref power (b18): 0 = internal reference is only powered if at least one dac is powered 1 = internal reference is always powered all dac commands code_all 1 0 0 0 0 0 0 0 code register data [11:4] code register data [3:0] x x x x writes data to all code registers load_all 1 0 0 0 0 0 0 1 x x x x x x x x x x x x x x x x updates all dac latches with current code register data code_ all_ load_all 1 0 0 0 0 0 1 x code register data [11:4] code register data [3:0] x x x x simultaneously writes data to all code registers while updating all dac registers no operation commands no operation 1 0 0 1 x x x x x x x x x x x x x x x x x x x x these commands will have no effect on the device 1 0 1 x x x x x x x x x x x x x x x x x x x x x 1 1 x x x x x x x x x x x x x x x x x x x x x x reserved commands: any commands not specifically listed above are reserved for maxim internal use only. maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
20 coden command the coden command (b[23:20] = 0000) updates the code register contents for the selected dac(s). changes to the code register content based on this command will not affect dac outputs directly unless the ldac is in a low state or the dac latch has been configured to be transparent. issuing the coden command with dac selection = all dacs is equivalent to code_all (b[23:16] = 10000000). see table 2 and table 3. loadn command the loadn command (b[23:20] = 0001) updates the dac register content for the selected dac(s) by upload- ing the current contents of the code register. the loadn command can be used with dac selection = all dacs to issue a software load for all dacs, which is equivalent to the load_all (b[23:16] = 10000001) command. see table 2 and table 3. coden_load_all command the coden_load_all command (b[23:20] = 0010) updates the code register contents for the selected dac(s) as well as the dac register content of all dacs. channels for which the code register content has not been modified since the last load to dac register or ldac operation will not be updated to reduce digital crosstalk. issuing this command with dac_address = all is equivalent to the code_all_load_all (b[23:16] = 1000001x) command. the coden_load_all com- mand by definition will modify at least one code reg- ister. to avoid this, use the loadn command with dac selection = all dacs or use the load_all com- mand. see table 2 and table 3. coden_loadn command the coden_loadn command (b[23:20] = 0011) updates the code register contents for the selected dac(s) as well as the dac register content of the selected dac(s). channels for which the code register content has not been modified since the last load to dac register or ldac operation will not be updated to reduce digital crosstalk. issuing this command with dac selection = all dacs is equivalent to the code_all_load_all command. see table 2 and table 3. code_all command the code_all command (b[23:16] = 10000000) updates the code register contents for all dacs. see table 2. load_all command the load_all command (b[23:16] = 10000001) updates the dac register content for all dacs by uploading the current contents of the code registers. see table 2. code_all_load_all command the code_all_load_all command (b[23:16] = 1000001x) updates the code register contents for all dacs as well as the dac register content of all dacs. see table 2. table 3. dac selection b19 b18 b17 b16 dac selected 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d x 1 x x all dacs 1 x x x all dacs maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
21 power command the max5713/max5714/max5715 feature a software- controlled power-mode (power) command (b[23:20] = 0100). the power command updates the power-mode settings of the selected dacs while the power settings of the rest of the dacs remain unchanged. the new power setting is determined by bits b[17:16] while the affected dac(s) are selected by bits b[11:8]. if all dacs are pow- ered down, the device enters a standby mode. in power-down, the dac output is disconnected from the buffer and is grounded with either one of the two selectable internal resistors or set to high impedance. see table 5 for the selectable internal resistor values in power-down mode. in power-down mode, the dac regis- ter retains its value so that the output is restored when the device powers up. the serial interface remains active in power-down mode. in standby mode, the internal reference can be pow- ered down or it can be set to remain powered-on for external use. also, in standby mode, devices using the external reference do not load the ref pin. see table 4. sw_reset and sw_clear command the sw_reset (b[23:16] = 01010001) and sw_clear (b[23:16] = 01010000) commands provide a means of issuing a software reset or software clear operation. use sw_clear to issue a software clear operation to return all code and dac registers to the zero-scale value. use sw_reset to reset all code, dac, and configuration registers to their default values. table 4. power (100) command format table 5. selectable dac output impedance in power-down mode b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 0 pd1 pd0 x x x x d c b a x x x x x x x x power command power mode: 00 = normal 01 = 1ki 10 = 100ki 11 = hi-z dont care multiple dac selection: 1 = dac selected 0 = dac not selected dont care default values (all dacs) ? 0 0 x x x x 1 1 1 1 x x x x x x x x pd1 (b17) pd0 (b16) operating mode 0 0 normal operation 0 1 power-down with internal 1ki pulldown resistor to gnd. 1 0 power-down with internal 100ki pulldown resistor to gnd. 1 1 power-down with high-impedance output. maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
22 config command the config command (b[23:20] = 0110) updates the ldac and load functions of selected dacs. issue the command with b16 = 0 to allow the dac latches to oper- ate normally or with b16 = 1 to disable the dac latches, making them perpetually transparent. mode settings of the selected dacs are updated while the mode settings of the rest of the dacs remain unchanged; dac(s) are selected by bits b[11:8]. see table 6. ref command the ref command updates the global reference setting used for all dac channels. set b[17:16] = 00 to use an external reference for the dacs or set b[17:16] to 01, 10, or 11 to select either the 2.5v, 2.048v, or 4.096v internal reference, respectively. if rf2 (b18) is set to zero (default) in the ref command, the reference will be powered down any time all dac channels are powered down (in standby mode). if rf2 (b18 = 1) is set to one, the reference will remain powered even if all dac channels are powered down, allowing continued operation of external circuitry. in this mode, the 1fa shutdown state is not available. see table 7. table 6. config command format table 7. ref command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 0 rf2 rf1 rf0 x x x x x x x x x x x x x x x x ref command 0 = off in standby 1 = on in standby ref mode: 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.0v dont care dont care default values ? 0 0 0 x x x x x x x x x x x x x x x x b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 all 0 0 ldb x x x x d c b a x x x x x x x x config command 0 = select individual dacs 1 = select all dacs config command 0 = normal 1 = transparent dont care multiple dac selection: 1 = dac selected 0 = dac not selected dont care default values (all dacs) ? 0 x x x x 1 1 1 1 x x x x x x x x maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
23 applications information power-on reset (por) when power is applied to v dd and v ddio , the dac out- put is set to zero scale. to optimize dac linearity, wait until the supplies have settled and the internal setup and calibration sequence completes (200fs, typ). power supplies and bypassing considerations bypass v dd and v ddio with high-quality ceramic capac- itors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead induc - tance. connect the gnd to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the max5713/max5714/max5715 gnd. carefully layout the traces between channels to reduce ac cross-coupling. do not use wire-wrapped boards and sockets. use shielding to minimize noise immu - nity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digital lines underneath the max5713/max5714/max5715 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl p 1 lsb, the dac guarantees no missing codes and is monotonic. if the magnitude of the dnl r 1 lsb, the dac output may still be monotonic. offset error offset error indicates how well the actual transfer function matches the ideal transfer function. the offset error is calculated from two measurements near zero code and near maximum code. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. zero-scale error zero-scale error is the difference between the dac output voltage when set to code zero and ground. this includes offset and other die level nonidealities. full-scale error full-scale error is the difference between the dac output voltage when set to full scale and the reference volt- age. this includes offset, gain error, and other die level nonidealities. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the converters specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
24 detailed functional diagram outa buffer a dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register a dac latch a 8- /1 0- /1 2- bit dac a outb buffer b dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register b dac latch b 8- /1 0- /1 2- bit dac b outc buffer c dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register c dac latch c 8- /1 0- /1 2- bit dac c outd buffer d dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register d dac latch d 8- /1 0- /1 2- bit dac d din sclk csb v ddio por (rdy) clr (ldac) spi serial interface ref 100ki r in internal/external reference (user option) max5713 max5714 max5715 () tssop package only v dd gnd maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
25 typical operating circuits dac c csb sclk din out gnd ldac v ddio v dd ref 100nf 100nf 4.7f max5713 max5714 max5715 clr note: unipolar operating circuit, one channel show n v ddio v dd dac c csb sclk din out gnd ldac v ddio v dd ref 100nf 100nf 4.7f r1 r2 r1 = r2 max5713 max5714 max5715 clr note: bipolar operating circuit, one channel show n v ddio v dd maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
26 ordering information note: all devices are specified over the -40c to +125c temperature range. +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *future productcontact factory for availability. chip information process: bicmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package resolution (bit) internal reference tempco (ppm/nc) max5713aud+t* 14 tssop 8 10 (typ) max5714aud+t* 14 tssop 10 10 (typ) max5715aaud+t 14 tssop 12 3 (typ),10 (max) max5715baud+t* 14 tssop 12 10 (typ) max5715awc+t 12 wlp 12 3 (typ),10 (max) package type package code outline no. land pattern no. 14 tssop u14+1 21-0066 90-0113 12 wlp w121b2+1 21-0009 refer to application note 1891 maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 27 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/12 initial release 1 11/12 updated the electrical characteristics, typical operating characteristics, typical operating characteristics, and the ordering information. 5, 7, 9, 10, 12, 13, 25, 26 2 1/13 updated the electrical characteristics and the ordering information. 7, 26 max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface

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